Warning!

Draft specifications and ECR’s are under the control of the subcommittee, if active. It is PICMG’s policy to prohibit claims of compliance with respect to a specification under development. Any such claims must be understood as applying to a draft, which is subject to change.

Errata 001 on R3.0

R2.0

SOW

Active

R2.0

Nov 15, 2006

Adopted

R2.0

Oct 8, 2008

Adopted

R2.0

August 8, 2010

Adopted

Warning!

Draft specifications and ECR’s are under the control of the subcommittee, if active. It is PICMG’s policy to prohibit claims of compliance with respect to a specification under development. Any such claims must be understood as applying to a draft, which is subject to change.

• Enhanced software connection architecture
• 3.3 volt 66 MHz support
• PCI-X compatibility
• Compliance language

The subcommittee was tasked with investigation of the existing standards for system management busses, but focusing primarily on the Philips I2C and Intel SMBus specifications. Following the investigation, deliverables to be voted on were to include a specification detailing the physical and electrical requirements of the system management bus as well as CompactPCI specific enhancements to the command set. A maximum of three, minimum of two bussed backplane pins would be required.

Where possible, we will seek to define OS-independent interfaces, but where necessary (especially for low-level interfaces) OS-specific approaches may be used. The initial specifications will address the interface to the platform (primarily ENUM# detection) and an alternate HS_CSR interface. We intend to use the PICMG-sponsored designs for these interfaces as the starting point for the Windows NT specifications. We will pursue a parallel effort for the same interface areas that is applicable to one or more Unix implementations.

• PICMG 2.1 R2.0
• Windows and Linux updates
• New OSs
• Redundant System Slot (RSS) API
• Switched PCI-PCI bridging support
• Hardware- and O/S-independent models of network-connected intelligent nodes
• Standards-based management of HS- and RSS-capable CompactPCI platforms
• IDSEL to GA mapping - ECR to PICMG 2.1

Users of CompactPCI have expressed interest in seeing standardization in the methods for processor boards to communicate with each other when co-existing in a shared PCI address space. This subcommittee will specify system topology and software mechanisms such that standard networking software run on boards from different vendors will interoperate with each other without modification by the end user. The approach taken will endeavor to include any microprocessor family (e.g. Pentium II, PowerPC, MIPS, etc.), be operating system agnostic, as well as qualify and specify minimal hardware requirements for in-band PCI signaling.

The PCI Telecom Mezzanine Card Specification defines pin locations on Pn3/Jn3 and Pn4/Jn4 for signals of the RMII, Ethernet PHY Management Interface, UTOPIA Level 1, UTOPIA Level 2, POS-PHY Level 2, and ECTF H.110 interfaces. Restrictions and relaxations of implementation requirements for these specifications are provided.

The CompactPCI Packet Switching Backplane provides a redundant, switched 10/100/1000 Ethernet network within a Compact PCI chassis providing connectivity between all slots using a star topology. It is intended to coexist with 64 bit CompactPCI and H.110. Special slot(s) for active switching fabric element(s), which may be redundant, are also specified.

The StarFabric Interconnect specification defines redundant, switched, high-speed point-to-point connectivity among some or all slots using StarFabric switch cards. The StarFabric interconnect will coexist with 64 bit PCI, CompactPCI and H.110. Optional compatibility with cPSB (PICMG 2.16) is specified. Systems that take advantage of StarFabric features can be designed to utilize existing single board computers (SBCs) and node cards.

Special slot(s) for active switching fabric element(s), which may be redundant, are also specified.

To ensure compatibility with existing CompactPCI 2.x products, only the standard hard metric 2mm connector will be utilized.

Changing any backplane connectors, such as was done on PICMG 2.20, is not being considered.

To expedite the development of this draft specification, the Technical Subcommittee will leverage existing PICMG work, such as PICMG 2.16 and 2.17, as much as possible. The Technical Subcommittee will perform signal integrity simulations to verify the performance of the resulting system for both best-case and worst-case conditions.

The CSMB specification augments PICMG 2.16, which describes a Gigabit IP switching and routing architecture overlaying CompactPCI, to create an additional 2.5 Gigabit interconnect for ATM-based and mixed protocol applications such as 3G wireless Node B base stations, radio network controllers, DSL equipment and media gateways.

The CSMB specification maintains maximum backwards compatibility with existing CompactPCI specifications (e.g., PICMG 2.0, 2.1, 2.9, 2.12, 2.13 and 2.16). The PICMG 2.20 CSMB fabric consists of differential serial signals capable of speeds to 1.25Gb/s, or 2.5Gb/s with a later improvement to 3.125Gb/s. Channels are arrayed in a "mesh" configuration that gives each slot full interconnects to every other slot, resulting in a distributed switch fabric architecture.

In this architecture, there is no fixed protocol switch/router, which results in significant advantages in cost, scalability and traffic management. Multiple protocols can be supported without adding complexity, while costs are only incurred when new mesh elements, network services, or subscribers are added.

• Tree system topology
• Connectors that support PCI Express Generation 1 signaling and potentially future generations of signaling
• A system slot definition that provides up to four high-bandwidth PCI Express Links, Rear I/O, and power to support current and future processor requirements
• A Type 1 Peripheral Slot definition, similar to the System Slot definition, that allows System Boards to operate in Peripheral Slots
• A Type 2 Peripheral Slot definition that allows a single high-bandwidth PCI Express Link and Rear I/O
• A Hybrid Peripheral Slot definition that supports both Type 2 Peripheral Boards and  legacy PICMG 2.0 32-bit CompactPCI Boards. 
• 6U definition of slots that support 6U System, Type 1, and Type 2 Boards that may have the J3, J4, and J5 connectors as defined in the PICMG 2.0 specification and its derivatives.
• An Optional Switch Slot.

This new specification adds the serial busses PCI Express, Ethernet, SATA, SAS and USB extensions to the CompactPCI family of specifications while preserving PCI bus connectivity. The specification defines the use of the previously reserved rear I/O pins for the 32-bit CompactPCI system slot with high-speed serial signals. To preserve interoperability with existing CompactPCI standards a fully compliant high speed connector is used for position J2 on the module, combined with the existing backplane connectors. As such it defines just the system slot extension, while for peripheral boards CompactPCI Serial, CompactPCI Express or PICMG 2.16 boards can be combined, depending on the interface.

PICMG 3.0 is intended for higher performance applications and is legacy free in terms of the direct electrical support for existing bus-based solutions such as PCI or H.110. The mechanical elements will be based on existing IEC 60297-3-xxx standards (Eurocard equipment practice) with additional requirements specified to meet the intended applications. A robust system management scheme will be defined. Equipment practice for power and cooling at the board and shelf level will be defined. Specific regulatory specifications will be referenced within PICMG 3.0 to give guidance to board, shelf and frame manufacturers building carrier grade equipment.

The PICMG 3.0 “core” specification will specify board, backplane and shelf mechanicals, power distribution and the connectivity required for system management. Multiple zones for connectors and their alignment and keying features will also be defined, and the physical mapping to a connector family will be specified. Specific fabric definitions will be undertaken on subsidiary specifications (PICMG 3.1, PICMG 3.2, etc.). In this manner, component interoperability will be defined by the combined PICMG 3.0 core specification and a subsidiary fabric specification. It is the intent to develop the core specification and subsidiary specifications as nearly in parallel as possible.

PICMG 3.0 R1.0 was conditionally ratified on December 30, 2002 for a period of one year which was later extended to January 21, 2004. 3004 has seen the release of PICMG 3.0 ECN001. Time has come to move towards a formal vote of the PICMG 3.0 specification. PICMG 3.0 R2.0 has been created which integrates ECN001, and an updated Appendix A which is believed to be free of unlicensable IPR.

The PICMG 3.2 specification will define how InfiniBand transport is mapped onto the PICMG 3.0 base. It will specify the link physical layers, protocols, and protocol mappings needed to implement multi-vendor, interoperable systems. Specification of addressing schemes, virtual lane mappings, initialization, keying, hot swap support, and hardware management will be included.

PICMG 3.2 will fully comply with, and build upon, the base provided by PICMG 3.0, including mechanical design, power, cooling and hardware management framework. The PICMG 3.2 specification is intended to coexist with and complement the other specifications based on PICMG 3.0, including PICMG 3.1 (using Ethernet backplane links) and PICMG 3.3 (using StarFabric backplane links).
 

PCI Express and StarFabric capabilities and implementations are highly aligned and can be interoperable through an adaptive bridging scheme. StarFabric utilizes a physical layer made up of pairs of 622Mbps differential signaling. PCI Express utilizes a physical layer with 4 times the bandwidth made up of pairs (lanes) of 2.5Gbps differential signaling with future speed upgrades possible. 

The specification will define switched, high-speed, low latency point-to-point connectivity among node, fabric (switch hub) and full mesh boards for PCI Express interconnects. Pin mappings for node and fabric cards/slots will be defined for the dual star, dual-dual star, and mesh fabric topologies defined in the PICMG 3.0 core specification.

• define how RapidIo signalling is utilized over the Extended Fabric Interface as defined in  PICMG 3.0
• define which configurations (1x Serial, 4x Serial, etc) are appropriate, and define the necessary electronic keying
• define and "extension" to the RapidIO specifications (if needed) appropriate for the PICMG 3.0 system environment

Although TDM support is the primary justification for developing a generic encapsulation protocol, other protocol encapsulation (such as ATM or POS) and the ability to manage these traffic flows is highly desirable for many communications applications and so the defined method should be flexible enough to support a wide variety of protocol encapsulations.

I-TDM stands for Internal TDM protocol. I-TDM is a multiplexed voice over packet protocol that is optimized for Voice LANs and Packet Backplanes (i.e. for connecting telephone equipment within the same chassis, room or building). I-TDM does not aim to be an end user protocol. It typically exists only inside the logical confines of a Voice Processing of Voice Switching System, hence the name Internal TDM. 

This is a subsidiary specification to the PICMG 3.0 specification and will define the standard approach for implementing ATCA based equipment which requires compliance with 400mm ANSI and ETSI equipment practices. 

It will define board depth adjustment, front transition module usage models, front access power entry modules, cable management and thermal requirements. It may optionally include usage definitions for shelf controller base fabric implementations.

The objective is to develop extensions to the AdvancedTCA architecture to make the platform more optimal for non-telecom applications including network data centers. 

Goals are:

• Maintain forward and backward compatibility with existing ATCA products
• Enhanced features for double-wide Boards
• Enhancements to power (and cooling)
• Scalable environmentals
• Allowances for double-sided Shelves
• Optional support for 10Gbps signaling on Base Interface provided that backwards compatibility can be maintained
• Add an additional example backplane topology

Deliverables will be either extensions to base PICMG 3.0 specification or supplemental specification early 2010.

This document represents the changes and additions made to the AMC.0 Spcification Release 1.0 and the ECN001.

This AMC.0 subsidiary specification is limited in scope to defining Port usage and Electronic-Keying (E-Keying) parameters for PCI Express. This specification includes definition for both AdvancedMC Modules and Carriers. AMC.1 defines a single Fat Pipe Link of 1, 2, 4, and 8 Lanes. It also defines a reference clock for use with the Fat Pipe Link.

By interconnecting a number of these AMCs into a single backplane, MicroTCA will serve as an optimal platform for many different applications. All mezzanines conforming to the AMC standard must fit directly into MicroTCA without modification. MicroTCA is optimized for smaller scale and more price sensitive applications and is therefore complementary to AdvancedTCA.

This specification, which must be used in conjunction with MicroTCA.0, provides the additional requirements necessary for a System with the additional capabilities to meet the more rugged requirements of outside plant telecom, industrial and aerospace environments. 
In addition it defines the test setups required to test MicroTCA components and Systems.

The MicroTCA.1 specification is focused on using forced-air as the cooling medium.

The original Computer-On-Module (COM) specification was adopted by PICMG in 2005, and was designed to reduce time-to-market on specialized platforms used in industrial, medical, military, scientific and telecommunication applications.

The COM Express Revision 2.0 specification allows developers to focus on their specialized I/O requirements, without worrying about the complex interactions of CPUs, RAM, Chipsets and other basic elements that occur on the module.  This recent revision helps to ensure that COM Express modules are prepared for future computer architectures while accommodating backward compatibly with older modules.  Some of the more important changes include:

• Smaller size

• Enhanced display support

• Faster Generation 2.0 PCI Express ports

• High definition audio

• USB client support

The revision also includes enhanced security and environmental monitoring support.

• Commercial and Military Applications

• Air cooled hardened form factors based upon the outline dimensions of the MicroTCA.3 module

• Environmental requirements similar to VITA47 air cooled and telecom

• Military Airborne, Shipboard, and Ground Mobile Equipment (general requirements; not program-specific)

• Hardened - Telecom, Machine Industry (Rotating  machine mounted) and Transport Industry (Railway; truck; ship; aircraft mounted)

• Commercial/non-Military Application while maintaining hot swappable feature

• Commercial solutions (forced air and/or conduction cooled/no fans)

• Commercial solutions (higher level of shock and vibration as per IEC60721-3-3 Class 3M4 or 3M7)

• Telco Industry Customer Premise Equipment

• Machine Industry (Rotating machine mounted)

• Transport Industry (Railway; truck; ship; aircraft mounted)

• Traffic Control

• Security

The working group shall strive for maximum compatibility with existing ATCA, µTCA and AMC specifications.

Various PICMG architectural specifications have electrical chapters that address the interconnect channel and define basic electrical requirements in terms of attenuation crosstalk and skew. It is now recognized that a more rigorous approach is needed to provide critical information that will allow potential adopters to evaluate the capability of an architecture for signaling at data rates beyond 3 Gigabits per second.

Creation of HPM.3, the DHCP-assigned Hardware Platform Management Parameters specification, to standardize the use of DHCP to assign management controller operational parameters, especially those related to IP addresses.

Creation of HPM.4, the Authenticating IPMC specification, to standardize IPMCs that can serve as a hardware root of trust for their intelligent FRUs. This effort aims to ensure that, where the HPM.4 architecture is adopted, intelligent FRUs participating in an xTCA system (and potentially, applications running thereon) are authorized to do so. The scope of HPM.4 will include sufficient definition of a supporting infrastructure (including cryptographic aspects) for authenticating IPMCs so that a compatible xTCA ecosystem can be established, much as has occurred for HPM.1.